The main memories of computer systems have been implemented with charge-based DRAM (dynamic RAM) for decades, and historical trends in technology scaling have delivered exponential improvements in storage density, overall capacity, and the storage-per-dollar ratio. The traditional scaling of DRAM technology to smaller feature sizes is in jeopardy, however, as fundamental physical limitations are likely to prevent DRAM scaling in the future. Challenges include the design of capacitive cells that retain sufficient charge to store the data and the mitigation of sub-threshold leakage through the access transistors. The cells must hold enough charge that the values can be reliably read back out at a later time. The minimal amount of charge required places a limitation on how small the storage cells can ultimately scale down. Due to the non-ideal behavior of transistors, charge continues to leak through the access transistors over time, leading to the need for even more charge to be stored as well as frequent refresh operations. This places a limit on how small the access transistors can be made while keeping refresh rates within practical limits.
Phase change memory (PCM), for example, has been proposed to augment, or even replace, DRAM because of its low idle power, scalability, and persistence. Two obstacles to the adoption of PCM are its relatively low cell lifetimes, which are projected to be on the order of 108 writes, and the high per-bit power cost of writing data. SEC (single error correction) and other Hamming codes and polynomial-based error correcting codes have been used for memories, but induce high wear.
One proposed mechanism to reduce power consumption and wear in PCM is to write only those cells for which the value to be written differs from the value currently stored. However, most error correcting codes introduce new cells that are likely to wear at a rate faster than the cells intended to be repaired. Wear-leveling may spread, but not eliminate, this added wear and does not address the additional power required to write codes.
Other recently-proposed error correction techniques for PCM, such as fine-grained error detection and correction using redundant pages, come at a cost of greater than 100% overheads for both space and write power.